Inspired by PA0NHC mini-whip, Jonathan Hare's Antennas for MSF 60 kHz LF, and Ferrite Sleeve Loop Antennas.
Seems to work quite well! This prototype shows about 140 pF of input(or parasitic) capacitance when the tuning capacitor is set to 0 pF. That could probably be improved on by better layout on a custom PCB.
Web-SDR located at Nastola
1:8 frequency distribution amplifier based on LMH6702 and LMH6609 op-amps.
In particular the power-supply section using a common-mode choke, a Murata BNX025 filter, and low-noise regulators LT1963 and LT3015 seems to work quite well. I also used ferrites (2 kOhm @ 100 MHz) as well as an RC-filter on all supply pins. Perhaps overkill? Performance with the intended AC/DC brick is still to be verified.
Measurements around 10 MHz show a 1 dB compression at over 14 dBm and an IP3 of around 27 to 30 dBm. The gain extends beyond 100 MHz with some gain-peaking.
Some measurements of residual phase-noise with a 3120A phase-meter, at 10 MHz. My earlier distribution amplifier required shielding with aluminium foil as well as powering from a lead-acid battery to achieve a reasonably quiet phase-noise spectrum. These measurements were done with lab power-supplies for +/-12 V to the board and without any shielding.
Finally some measurements of gain vs. frequency with a Rigol spectrum analyzer.
A new pulse distribution amplifier for 1PPS distribution.
The input is fed to a LT1711 comparator triggering at 1.0 V (set by reference ADR423). This edge is buffered by 74AC14 before 1:8 fan-out to output-stages with three 74AC04 inverters in parallel driving the outputs.
Preliminary measurements show around 200ps channel-to-channel propagation skew - to be improved on by further trace-length matching or tuning. More measurements to follow.
A new distribution amplifier design featuring a 1PPS pulse distribution amplifier (PDA) and a 5/10 MHz frequency distribution amplifier (FDA).
1U 150mm deep rack-enclosure from Schaeffer. Prototype PCBs without soldermask or silkscreen from Prinel. Both the FDA and PDA boards have 1:8 fan-out with 9 BNC (optionally SMA) connectors spaced 16mm apart. The boards fit comfortably side-by side on a 19" rack panel. Some funky BNC-cables with unusually large connectors may not fit side-by-side 16mm apart - a price to pay for the compact design. The plan is to use an +/-12 AC/DC brick power-supply (not shown) which fits in the back of the enclosure.
Detailed posts on the PDA and FDA boards to follow.
Holy megacycles Batman! This thing is made for hacking. You telnet into the thing, delete one line in an XML config file, and then reboot. Whiskey-Tango-Foxtrot!?
Here's how the screen looks before and after, and a view of the 120 MHz signal on the scope. There's a bit of amplitude ripple as you sweep up from around 50 MHz.
For various experiments I got an USRP N210. Here's how to get going with gnuradio.
By default it shows up at 192.168.10.2, so configure your PC eth-interface on 192.168.10.XXX. Now
$ uhd_find_devices
Should find the device:
--------------------------------------------------
-- UHD Device 0
--------------------------------------------------
Device Address:
type: usrp2
addr: 192.168.10.2
However uhd_usrp_probe suggest upgrading the firmware and FPGA image, so we do that by:
$ sudo /usr/lib/uhd/utils/uhd_images_downloader.py
$ sudo /usr/bin/uhd_image_loader --args="type=usrp2,addr=192.168.10.2"
and after power-cycling the device we now get (in addition to a long description of the RX and TX interfaces or installed daughter-boards):
$ uhd_usrp_probe
FW Version: 12.4
FPGA Version: 11.1
To show that it works in gnuradio a simple USRP-source can be connected to a QT GUI Sink (or QT GUI Frequency Sink) that visualizes RX I/Q samples:
The source needs to be configured with "addr=192.168.10.2" and it uses the samp_rate, freq, and gain variables.
The USRP now samples at 100 MS/s, digitally downconverts a bandwidth samp_rate around a center frequency freq, and streams the samples over Ethernet to the gnuradio source node. When setting freq=10e6 and samp_rate=200k (the minimum possible!?) and applying a 10.020 MHz sine-wave to the RF1-input we get this:
With a signal that seems close to maximum amplitude the dB-scale shows a peak at -16 dB, and without any signal applied the noise-floor close to the center frequency dips just below -140 dB rising to -135 dB at 20 kHz offset.
Awesome stuff! The 200 kS/s samples from one I/Q channel produce about 800 kB/s of Ethernet traffic.
Stay tuned for more SDR updates in the near future!
I put together a PICDIV frequency divider for use with a Rubidium clock.
I used an LTC6957-3 to convert the 10 MHz sine-wave from the clock to a CMOS logic signal (square wave). The LTC6957-3 has two outputs, one is routed to a BNC connector output, the other is used as the clock for a PIC12F675. The PIC runs pd09.asm which outputs a 20 us long pulse every second - i.e. it divides the 10 MHz input frequency by 1e7. The PIC is programmed through a 5-pin 100 mil ICSP header.
Here are some test-signals with a SRS PRS-10 as the source, and recorded on a Rigol scope.
The outputs behave as expected, but the 1PPS from the PIC is only 700 mVpp into 50R - a bit low. When terminated to 1 MOhm the rise-time is much worse so this is best avoided. Perhaps a buffer or level-translator would be a good addition.
Finally phase-noise measurements on the 10 MHz CMOS output, performed with a 3120A phase-noise probe.
I tried shielding the circuit with aluminium foil and powering it from a +12 VDC lead-acid battery - however the three measurement runs look roughly similar. Perhaps the LM317 regulator is not a great choice here, and both the LTC sine-to-square chip and the PIC should have more bypass caps and decoupling (inductors, ferrites?). In any case the phase-noise is 10-20x better than the measurement noise from a typical counter (SR620 or 53230A), so any issues only show up with high-end phase-noise probes.
Short notes on Rigol DS2072A upgrade following bineteri's step-by-step post.
Frequency response before and after:
Python code for plot:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 | import matplotlib.pyplot as plt import math # rigol ds2072a frequency response test # AW2015-12-28 bf=[10, 20, 40, 60, 70, 80, 100, 130, 160, 200, 250, 300, 400, 500, 600, 700, 800, 900, 1000] before=[1008, 992, 944, 880, 848, 808, 728, 624, 560, 456, 396, 332, 224, 100, 25, 18, 1.5, 1, 1] af=[10, 20, 40, 60, 70, 80, 100, 130, 160, 200, 250, 300, 350, 400, 450, 500, 550, 600, 700, 800, 900, 1000 ] after=[1000, 984, 984, 984, 992, 976, 976, 944, 928, 904, 888, 856, 760, 656, 556, 308, 20, 30, 40, 1, 1.5, 2] # for comparison RC-filter response for 70MHz and 300MHz rc70 = [ 1000.0 / math.sqrt( 1+ pow( f/70.0, 2 ) ) for f in bf] rc300 = [ 1000.0 / math.sqrt( 1+ pow( f/300.0, 2 ) ) for f in bf] plt.figure() plt.loglog(bf, before,'b',label='Before') plt.loglog(bf, rc70 ,'b--',label='70 MHz RC-filter response') plt.loglog(af, after,'r',label='After') plt.loglog(bf, rc300,'r--',label='300 MHz RC-filter response') plt.title('Rigol DS2072A update, AW2015-12-28\nSignal generator: HP8647A (+3.8 dBm) into CH1 50 Ohm DC-coupled') plt.ylabel('CH1 Vpp (mV)') plt.xlabel('Frequency (MHz)') plt.grid(True, which="both") plt.ylim((1,1100)) plt.legend(framealpha=0.6, loc='lower left') plt.show() |
I wasn't entirely happy with my frequency distribution amplifier prototype measurements, so I decided to do some SPICE simulations.
Here is a circuit close to the original TADD-1 design, configured for a voltage gain of 2, which when loaded with 50R corresponds to unity gain or 0 dB.
The main contribution to the noise floor at 10 MHz is by the AD8055 op-amp (roughly 3/4ths), with the gain-resistors R4 and R5 also contributing (roughly 1/4th). The simulation gives an output-referred noise-floor of 17.4 nV/sqrt(Hz) between around 100kHz and 20MHz. At low frequencies the 1/f noise of the op-amp dominates. The large 47k bias-resistors R2 and R3 are not bypassed/filtered in this design and they contribute significantly at low frequencies.
17.4nV/sqrt(Hz) is -142 dBm/Hz. This is a one-sided spectrum so we subtract 3 dB to get a single-sideband number, and then another 3 dB since noise is divided equally into AM and PN. This gives a best-case PN of -148 dBc/Hz for a 0 dB input/output power. In my measurements I got about -157 dBc/Hz with +7 dBm output.
The v2 design uses the ADA4899-1 op-amp instead of the AD8055. This improves the op-amp input voltage noise floor from 6 nV/sqrt(Hz) to 1 nV/sqrt(Hz) while also reducing the near-DC voltage noise by more than ten-fold.
The simulation for the ADA4899-1 design shows an output-referred noise floor of 4 nV/sqrt(Hz) from 10 kHz to 20 MHz. This corresponds to about -155 dBm/Hz, a 12.7 dB improvement over the original design. The SPICE model for the ADA4899-1 does not include 1/f noise so I have estimated it with a dashed line. I have tried to minimize the resistor noise with reduced resistance values for the gain-setting resistors R4, R5, and a bypassed (C5) 'T'-circuit for the DC-bias (R2, R3, R9).
The theoretical PN floor with 0 dBm signal is now -161 dBc/Hz (again 13 dB better than for the original design).
Here is a figure that compares the two simulations:
These figures show an AC sweep response for the SPICE simulations:
Further ideas and ToDo:
Constructive comments are welcome!